In conventional technologies, there are ways of controlling power dissipation by a processing chip. For instance, states are introduced, such as on full, on slower, clock off and chip off. Examples are the “nap, doze, sleep and suspend” states in implementations of the PowerPC architecture, and the “sleep” and “deeper sleep” states in enhanced Intel SpeedStep® power management for processors.
However, there are a number of problems with the conventional technologies when applied to multiprocessor systems. First, in prior systems, power management modes are not software accessible. In typical implementations the system controller is responsible for using the power management capabilities of the chip to effect power management. This is disadvantageous because though the system controller can respond to such system aspects as chip or module temperature, a system controller has limited information about the tasks the processors perform. In some microprocessors that perform emulation this problem has been partially overcome by providing a power management interface to the hardware emulation layer. This has been done in processors by Transmeta® corporation. Because the emulation layer can observe a level of software activity, power management can be done in response to both external measures such as chip temperature and software activity as monitored by the emulation software. This enables such processors to save additional power when only light tasks, such as DVD playback, are performed.
However, because the power management states are not available to the operating system or a hypervisor, additional opportunities for power management, such as managing power by scheduling tasks and levels of activity of multiple tasks is not performed. This capability is especially important in multiprocessor systems where an operating system or hypervisor has the freedom to rebalance tasks (threads) across multiple processors in order to improve overall power or power and heat distribution throughout the chip or system. In symmetric multiprocessor systems, even greater opportunities for task placement or migration and hence power balancing exist.
Furthermore, conventional technologies, have not successfully implemented a control system that is individually directed to individual processors of a multiprocessor system. Although “system wide” implementations have been created that allow for external control of the entire system with the microprocessing chips in lock-step, there is no control shown for individual processors in a multi-processor system.
Furthermore, system-on-chip designs that combine the processor with such units as memory controllers and bus controllers require extending power management techniques beyond the processors themselves. Also, modern microprocessors may allow for more detailed power management of units within a single processor core. Hence a more hierarchical approach, where power management states can apply to collections of units, including processors, and subunits of processors, is desirable.
Therefore, there is a need for an architected power control interface that can be used by a hypervisor or operating system in a multiprocessing environment that addresses at least some of the concerns associated with conventional power management control in multiprocessor and system-on-chip environments.